The present invention relates generally to a semiconductor device and more specifically to a semiconductor device including an insulated gate field effect transistor (IGFET) having a source and drain with differing impurity concentrations and its manufacturing method.
Large scale integrated semiconductor devices include semiconductor memory devices and semiconductor logic devices. Many of these semiconductor devices employ MOSFETs (metal oxide semiconductor field effect transistors) due to their manufacturability and performance to provide highly integrated circuits. Semiconductor memories include DRAMs (dynamic random access memories) and SRAMs (static random access memories). DRAMs provide a smaller bit/area and thus have reduced costs and are employed in a variety of data storage applications.
A DRAM includes a plurality of memory cells arranged in an array configuration. Each memory cell includes a memory cell transistor and a memory cell capacitor (capacitor element). Information is stored in a memory cell by storing electric charges on a memory cell capacitor. A memory cell transistor is turned on to select a memory cell to provide access to the memory cell capacitor to read data from or write data to the memory cell capacitor. A memory cell transistor in a DRAM is typically a MOSFET.
As is well known, a MOSFET includes a source area and a drain area, both being formed with a predetermined conductivity type on a semiconductor substrate. A MOSFET also includes a gate electrode formed on a gate insulating film over a channel area between the source area and drain area. An impedance path between the source area and drain area is controlled by applying a control voltage to the gate electrode. In this way, the conductivity of the channel area is controlled.
Japanese Patent Laid-Open No. 66861/1985 discloses a manufacturing method for a conventional MOSFET. FIGS. 1A-1C are cross-sectional views illustrating various processing steps for a conventional MOSFET as disclosed in Japanese Patent Laid-Open No. 66861/1985.
Referring now to FIG. 1A, a selective oxidation method is used to form a field oxide film 102 on the surface of a P-type silicon substrate 101. A CVD oxide film 103 and gate oxide film 104 are then formed on a device formation area. A gate electrode 105 is then formed on a side wall of CVD oxide film 103 to cover a part of gate oxide film 104.
Referring now to FIG. 1B, CVD oxide film 103 and gate oxide film 104 are etched and removed to leave behind only gate electrode 105 and gate oxide film 104 located just under gate electrode 105. An N-type impurity, such as arsenic (As), for example, is then implanted with a low dose through ion implantation using gate electrode 105 as a mask.
Referring now to FIG. 1C, a CVD oxide film 106 is then formed on a side wall of gate electrode 105. Then an N-type impurity, such as arsenic (As), for example, is implanted with a high dose through ion implantation using gate electrode 105 and CVD oxide film 106 as a mask. The ion doped arsenic is then diffused by being subjected to a heat treatment to form a LDD (lightly doped drain) structure MOSFET including an N+ type (high concentration N-type conductivity) area and an Nxe2x88x92 type (low concentration N-type conductivity) area.
The conventional manufacturing method for a semiconductor device as described above has a drawback in that the source area and the drain area are both formed with the same impurity concentration distribution. By doing so, the performance when operating in in some applications may be limited.
In the conventional manufacturing method for a MOSFET disclosed in Japanese Patent Laid-Open No. 66861/1985, the source area and drain area are formed in the same process by implanting an impurity ion in a common process step. By doing so, the impurity concentration distributions in these areas are symmetrical. In this case, the source area and the drain area are compatible with a basic or typical performance of a MOSFET. However, in some applications a MOSFET having impurity concentration distributions that are the same in the source area and drain area may have drawbacks.
In light of the above discussion, it would be desirable to provide a semiconductor device including an insulated gate field effect transistor (IGFET), such as a MOSFET, that includes a source/drain area that has a lower impurity concentration distribution than the other source/drain area. It would also be desirable to provide such an IGFET in a memory cell of a semiconductor memory device, such as a DRAM. It would also be desirable to provide a manufacturing method for the semiconductor device.
A semiconductor device according to the present embodiments may include an IGFET (insulated gate field effect transistor). An IGFET may include a source/drain area having an impurity concentration distribution that may be formed shallower at a higher concentration than the impurity concentration distribution in another source/drain area. A gate oxide film may include a first gate oxide film adjacent to a source/drain area and a second gate oxide film adjacent to another source drain area. A second gate oxide film may be thinner than a first gate oxide film. An impurity concentration distribution of a second channel impurity area under a second gate oxide film may be at a higher concentration than an impurity concentration distribution of a first channel impurity area under a first gate oxide film. In this way, an electric field at a PN junction of a source/drain area may be reduced.
According to one aspect of the embodiments, a semiconductor device may include a first source/drain area of a second conductivity type formed in a semiconductor area of a first conductivity type. A second source/drain area of the second conductivity type may be formed in the semiconductor area. A gate electrode may be formed on a gate insulating film on a channel area disposed between the first source/drain area and the second source/drain area. The gate insulating film may include a first gate insulating film formed on a first channel area portion and a second gate insulating film formed on a second channel area portion. A second type impurity concentration distribution in the first source/drain area may be different from the second type impurity concentration distribution in the second source/drain area. A thickness of the first gate insulating film maybe different from a thickness of the second gate insulating film.
According to another aspect of the embodiments, a semiconductor device may include a first source/drain area of a second conductivity type formed in a semiconductor area of a first conductivity type. A second source/drain area of the second conductivity type may be formed in the semiconductor area. A gate electrode may be formed on a gate insulating film on a channel area disposed between the first source/drain area and the second source/drain area. The channel area may include a first a first channel area and a second channel area. A second type impurity concentration distribution in the first source/drain area may be different from the second type impurity concentration distribution in the second source/drain area. A first type impurity concentration distribution of the first channel area may be different from the first type impurity concentration distribution of the second channel area.
According to another aspect of the embodiments, a first type impurity concentration distribution in the first channel area portion may be different from the first type impurity concentration distribution in the second channel area portion.
According to another aspect of the embodiments, the first gate electrode and the second gate electrode maybe formed in a side wall configuration.
According to another aspect of the embodiments, the first gate electrode and the second gate electrode may be electrically connected through a third gate electrode.
According to another aspect of the embodiments, an insulating film may be formed between the first gate electrode and the second gate electrode.
According to another aspect of the embodiments, the first channel area portion may be adjacent to the first source/drain area. The second channel area portion may be adjacent to the second source/drain area. The second type impurity concentration in the first source/drain area may be lower than the second type impurity concentration in the second source/drain area. The first gate insulating film may be thicker than the second gate insulating film.
According to another aspect of the embodiments, a capacitor may be electrically connected to the first source/drain area. A bit line may be electrically connected to the second source/drain area. The second type impurity concentration in the first source/drain area may be lower than the second type impurity concentration in the second source/drain area.
According to another aspect of the embodiments, the second source/drain area may provide a common source/drain area for a pair of memory cells.
According to another aspect of the embodiments, the gate insulating film may include a first gate insulating film formed on the first channel area and a second gate insulating film formed on the second channel area. A thickness of the first gate insulating film may be different from a thickness of the second gate insulating film. The first gate electrode may be formed on the first gate insulating film. The second gate electrode may be formed on the second gate insulating film.
According to another aspect of the embodiments, the first channel area may be adjacent to the first source/drain area. The second channel area may be adjacent to the second source/drain area. The second type impurity concentration in the first source/drain area may be lower than the second type impurity concentration in the second source/drain area. The first type impurity concentration in the first channel area may be lower than the first type impurity concentration in the second channel area.
According to another aspect of the embodiments, a semiconductor device may include a first source/drain area of a second conductivity type formed in a semiconductor area of a first conductivity type. A second source/drain area of the second conductivity type may be formed in the semiconductor area. A gate electrode may be formed on a gate insulating film on a channel area between the first source/drain area and the second source/drain area. A manufacturing method for the semiconductor device may include the steps of forming a first insulating film on the semiconductor area, forming a first mask layer at a predetermined position on the first insulating film, forming the first source/drain area in the semiconductor area with the first mask layer, forming a second mask layer on the first source/drain area, forming a first channel area of the first conductivity type adjacent to the first source/drain area with the second mask layer, forming a first gate electrode on the side walls of the second mask layer, forming a second channel area of the first conductivity type at an essentially central portion of the first channel area with the first gate electrode providing a mask, forming a second insulating film on the second channel area, forming a second gate electrode over the second insulating film and separated from the first gate electrode by a mediating insulating film, forming the second source/drain area at a substantially central portion of the second channel area with the second gate electrode providing a mask, and forming a third gate electrode providing an electrical connection for the first gate electrode and the second gate electrode. The second insulating film may have a different thickness than the first insulating film.
According to another aspect of the embodiments, a second type impurity concentration distribution of the first source/drain area may be different than the second type impurity concentration distribution of the second source/drain area.
According to another aspect of the embodiments, a first type impurity concentration distribution of the first channel area may be different from the first type impurity concentration distribution of the second channel area.
According to another aspect of the embodiments, a manufacturing method of a semiconductor device may include forming a capacitor electrically connected to the first source/drain area.
According to another aspect of the embodiments, a second type impurity concentration of the first source/drain area may be lower than the second type impurity concentration of the second source/drain area.